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Lattice Leverages FD-SOI for New Low Power FPGAs

In many of the world’s electronic applications today, low power is the name of the game. However, high levels of integration and device scaling have created a power/performance/reliability tradeoff that has mostly halted traditional power scaling methods. 

One technology used in the industry to mitigate this tradeoff is fully depleted silicon-on-insulator (FD-SOI) technology which can operate at 75% lower power as compared to a bulk CMOS process. Lattice Semiconductor continues to reap the benefits of FD-SOI with its newest FPGA offerings. These offerings claim to be some of the company’s lowest power yet, and they cite FD-SOI as a key source. 

FD-SOI
For a while, this mathematical technique worked; however, as threshold voltages decreased, so did the sub-threshold region. Eventually, this led to increased leakage currents. Essentially, the transistors do not turn off very well. At the same time, mass integration resulted in billions of transistors on a single chip.  

Suddenly the sum of individual threshold leakages was far from trivial, and designers could no longer afford to lower supply voltage and threshold voltages. 

To address this need, many semiconductor companies have turned to FD-SOI technology. FD-SOI technology is very similar to conventional bulk CMOS but crucially adds two features: an extremely thin transistor channel and an insulating buried oxide underneath the channel. This extremely thin transistor channel can be beneficial since it doesn’t need to be doped (hence fully depleted). 

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